/******************************************************************************
 copyright (C), 2018, hisilicon tech. co., ltd.
******************************************************************************
file name     : hal_media_freq.c
version       : initial draft
author        : hisilicon multimedia software group
created       : 2018/10/18
last modified :
description   :
function list :
******************************************************************************/
#include "hi_osal.h"
#include "hi_math.h"
#include "hi_debug.h"

#include "hal_media_frq.h"
#include "pm_drv_comm.h"

#define CRG_ADDR_MEDIA1 0x1201004c
#define CRG_ADDR_MEDIA2 0x12010054
#define CRG_ADDR_MEDIA3 0x12010044
#define CRG_ADDR_MEDIA4 0x12010080

const hi_media_freq media_profile[3] = {  // 3: max num media profile
    {
        .vi[0]  = VI_F300M,
        .pipe_be = PIPEBE_F300M,
        .vpss = VPSS_F300M,
        .vedu = VEDU_F396M,
        .jpge = JPGE_F400M,
        .vdp = VDP_F198M,
        .vgs = VGS_F500M,
        .gdc = GDC_F475M,
        .tde = TDE_F150M,
    },
    {
        .vi[0]  = VI_F396M,
        .pipe_be = PIPEBE_F300M,
        .vpss = VPSS_F300M,
        .vedu = VEDU_F396M,
        .jpge = JPGE_F400M,
        .vdp = VDP_F198M,
        .vgs = VGS_F500M,
        .gdc = GDC_F475M,
        .tde = TDE_F150M,
    },
    {
        .vi[0]  = VI_F600M,
        .pipe_be = PIPEBE_F340M,
        .vpss = VPSS_F300M,
        .vedu = VEDU_F396M,
        .jpge = JPGE_F400M,
        .vdp = VDP_F198M,
        .vgs = VGS_F500M,
        .gdc = GDC_F475M,
        .tde = TDE_F150M,
    },
};

#define pm_readl(x) (*((volatile int *)(x)))
#define pm_writel(v, x) (*((volatile int *)(x)) = (v))

static inline void hi_reg_write32(hi_u32 value, hi_u32 mask,
                                 hi_u32 addr)
{
    hi_u32 t;
    t = pm_readl((const volatile void *)addr);
    t &= ~mask;
    t |= value & mask;
    pm_writel(t, (volatile void *)addr);
}

static inline void hi_reg_read(hi_u32 *pvalue, hi_u32 addr)
{
    *pvalue = pm_readl((const volatile void *)addr);
}


hi_s32 pm_hal_get_misc_policy(void)
{
    return (hi_s32)HI_PM_MISC_POLICY_NONE;
}

/*----------------media freq config--------------------------------*/

static hi_s32 pm_hal_set_vicap_freq(const hi_vi_freq vi_freq)
{
    switch (vi_freq) {
        case VI_F214M:
            hi_reg_write32(0, 0x7, CRG_ADDR_MEDIA1);  // 0:VI_F214M   0x7:?
            break;
        case VI_F300M:
            hi_reg_write32(1, 0x7, CRG_ADDR_MEDIA1);  // 1: VI_F300M  0x7:?
            break;
        case VI_F340M:
            hi_reg_write32(4, 0x7, CRG_ADDR_MEDIA1);  // 4: VI_F340M  0x7:?
            break;
        case VI_F396M:
            hi_reg_write32(5, 0x7, CRG_ADDR_MEDIA1);  // 5: VI_F396M  0x7:?
            break;
        case VI_F500M:
            hi_reg_write32(2, 0x7, CRG_ADDR_MEDIA1);  // 2: VI_F500M  0x7:?
            break;
        case VI_F600M:
            hi_reg_write32(3, 0x7, CRG_ADDR_MEDIA1);  // 3: VI_F600M  0x7:?
            break;
        default:
            osal_printk("set VI0 freq %d error.\n", vi_freq);
            return MPP_EN_PM_ILLEGAL_PARAM;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_get_vicap_freq(hi_vi_freq *vi_freq)
{
    hi_u32 vi0_freq;
    hi_reg_read(&vi0_freq, CRG_ADDR_MEDIA1);
    vi0_freq &= 0x7;  // 0x7:?
    switch (vi0_freq) {
        case 0:  // 0:VI_F214M
            *vi_freq = VI_F214M;
            break;
        case 1:  // 1:VI_F300M
            *vi_freq = VI_F300M;
            break;
        case 4:  // 4:VI_F340M
            *vi_freq = VI_F340M;
            break;
        case 5:  // 5:VI_F396M
            *vi_freq = VI_F396M;
            break;
        case 2:  // 2:VI_F500M
            *vi_freq = VI_F500M;
            break;
        case 3:  // 3:VI_F600M
            *vi_freq = VI_F600M;
            break;
        default:
            osal_printk("get VI0 freq %d error.\n", vi0_freq);
            return HI_FAILURE;
    }
    return HI_SUCCESS;
}


static hi_s32 pm_hal_set_vi_pipe_be_freq(hi_pipebe_freq pipe_be_freq)
{
    switch (pipe_be_freq) {
        case PIPEBE_F214M:
            hi_reg_write32(0 << 14, 0x1f << 14, CRG_ADDR_MEDIA2);  // 14:? 0x1f:?
            break;
        case PIPEBE_F300M:
            hi_reg_write32(1 << 14, 0x1f << 14, CRG_ADDR_MEDIA2); // 1<<14:? 0x1f:?
            break;
        case PIPEBE_F340M:
            hi_reg_write32(2 << 14, 0x1f << 14, CRG_ADDR_MEDIA2); // 2<<14:? 0x1f:?
            break;
        case PIPEBE_FVI:
            hi_reg_write32(8 << 14, 0x1f << 14, CRG_ADDR_MEDIA2); // 8<<14:? 0x1f:?
            break;

        default:
            osal_printk("set PIPEBE0 freq %d error.\n", pipe_be_freq);
            return MPP_EN_PM_ILLEGAL_PARAM;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_get_vi_pipe_be_freq(hi_pipebe_freq *pipe_be_freq)
{
    hi_u32 pipebe0_freq;
    hi_reg_read(&pipebe0_freq, CRG_ADDR_MEDIA2);
    pipebe0_freq &= (0x1f << 14); // 0x1f << 14:?
    pipebe0_freq >>= 14; // 14:?
    switch (pipebe0_freq) {
        case 0: // 0: PIPEBE_F214M
            *pipe_be_freq = PIPEBE_F214M;
            break;
        case 1: // 1: PIPEBE_F300M
            *pipe_be_freq = PIPEBE_F300M;
            break;
        case 2: // 2: PIPEBE_F340M
            *pipe_be_freq = PIPEBE_F340M;
            break;
        case 8:  // 8: PIPEBE_FVI
            *pipe_be_freq = PIPEBE_FVI;
            break;
        default:
            osal_printk("get PIPEBE0 freq %d error.\n", pipebe0_freq);
            return HI_FAILURE;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_set_vpss_freq(hi_vpss_freq vpss_freq)
{
    switch (vpss_freq) {
        case VPSS_F214M:
            hi_reg_write32(0 << 5, 0x7 << 5, CRG_ADDR_MEDIA1);  // 0 << 5, 0x7 << 5:?
            break;
        case VPSS_F300M:
            hi_reg_write32(1 << 5, 0x7 << 5, CRG_ADDR_MEDIA1);  // 1 << 5, 0x7 << 5: ?
            break;
        case VPSS_F396M:
            hi_reg_write32(2 << 5, 0x7 << 5, CRG_ADDR_MEDIA1);  // 2 << 5, 0x7 << 5: ?
            break;
        default:
            osal_printk("set VPSS freq %d error.\n", vpss_freq);
            return MPP_EN_PM_ILLEGAL_PARAM;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_get_vpss_freq(hi_vpss_freq *vpss_freq)
{
    hi_u32 tmp_vpss_freq;
    hi_reg_read(&tmp_vpss_freq, CRG_ADDR_MEDIA1);
    tmp_vpss_freq &= (0x7 << 5);  // 0x7 << 5: ?
    tmp_vpss_freq >>= 5; //  5: ?
    switch (tmp_vpss_freq) {
        case 0: //  0: VPSS_F214M
            *vpss_freq = VPSS_F214M;
            break;
        case 1: //  1: VPSS_F300M
            *vpss_freq = VPSS_F300M;
            break;
        case 2: //  2: VPSS_F396M
            *vpss_freq = VPSS_F396M;
            break;
        default:
            osal_printk("get VPSS freq %d error.\n", tmp_vpss_freq);
            return HI_FAILURE;
    }
    return HI_SUCCESS;
}


static hi_s32 pm_hal_set_vedu_freq(hi_vedu_freq vedu_freq)
{
    switch (vedu_freq) {
        case VEDU_F396M:
            hi_reg_write32(1 << 10, 0x7 << 10, CRG_ADDR_MEDIA1);  // 1 << 10, 0x7 << 10: ?
            break;
        case VEDU_F500M:
            hi_reg_write32(2 << 10, 0x7 << 10, CRG_ADDR_MEDIA1);  // 2 << 10, 0x7 << 10: ?
            break;
        case VEDU_F594M:
            hi_reg_write32(3 << 10, 0x7 << 10, CRG_ADDR_MEDIA1);  // 3 << 10, 0x7 << 10: ?
            break;
        default:
            osal_printk("set VEDU freq %d error.\n", vedu_freq);
            return MPP_EN_PM_ILLEGAL_PARAM;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_get_vedu_freq(hi_vedu_freq *vedu_freq)
{
    hi_u32 tmp_vedu_freq;
    hi_reg_read(&tmp_vedu_freq, CRG_ADDR_MEDIA1);
    tmp_vedu_freq &= (0x7 << 10);  // 0x7 << 10: ?
    tmp_vedu_freq >>= 10;  //  10: ?
    switch (tmp_vedu_freq) {
        case 1:  //  1: VEDU_F396M
            *vedu_freq = VEDU_F396M;
            break;
        case 2:  //  2: VEDU_F500M
            *vedu_freq = VEDU_F500M;
            break;
        case 3:  //  3: VEDU_F594M
            *vedu_freq = VEDU_F594M;
            break;
        default:
            osal_printk("get VEDU freq %d error.\n", tmp_vedu_freq);
            return HI_FAILURE;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_set_jpge_freq(hi_jpge_freq jpge_freq)
{
    return HI_SUCCESS;
}

static hi_s32 pm_hal_get_jpge_freq(hi_jpge_freq *jpge_freq)
{
    *jpge_freq = JPGE_F400M;
    return HI_SUCCESS;
}

static hi_s32 pm_hal_get_vgs_freq(hi_vgs_freq *vgs_freq)
{
    hi_u32 tmp_vgs_freq;
    hi_reg_read(&tmp_vgs_freq, CRG_ADDR_MEDIA1);
    tmp_vgs_freq &= (0x7 << 13);  //  0x7 << 13: ?
    tmp_vgs_freq >>= 13;  //  13: ?
    switch (tmp_vgs_freq) {
        case 0:  //  0: VGS_F300M
            *vgs_freq = VGS_F300M;
            break;
        case 1:  //  1: VGS_F396M
            *vgs_freq = VGS_F396M;
            break;
        case 2:  //  2: VGS_F500M
            *vgs_freq = VGS_F500M;
            break;
        default:
            osal_printk("get VGS freq %d error.\n", tmp_vgs_freq);
            return HI_FAILURE;
    }
    return HI_SUCCESS;
}


static hi_s32 pm_hal_set_vgs_freq(hi_vgs_freq vgs_freq)
{
    switch (vgs_freq) {
        case VGS_F300M:
            hi_reg_write32(0 << 13, 0x7 << 13, CRG_ADDR_MEDIA1);  //  0 << 13, 0x7 << 13: ?
            break;
        case VGS_F396M:
            hi_reg_write32(1 << 13, 0x7 << 13, CRG_ADDR_MEDIA1);  //  1 << 13, 0x7 << 13: ?
            break;
        case VGS_F500M:
            hi_reg_write32(2 << 13, 0x7 << 13, CRG_ADDR_MEDIA1);  //  2 << 13, 0x7 << 13: ?
            break;
        default:
            osal_printk("set VGS freq %d error.\n", vgs_freq);
            return MPP_EN_PM_ILLEGAL_PARAM;
    }
    return HI_SUCCESS;
}


static hi_s32 pm_hal_get_vdec_freq(hi_vdh_freq *vdh_freq)
{
    hi_u32 tmp_vdh_freq;
    hi_reg_read(&tmp_vdh_freq, CRG_ADDR_MEDIA2);
    tmp_vdh_freq &= (0x1f << 6);  //  0x1f << 6: ?
    tmp_vdh_freq >>= 6;  //  6: ?
    switch (tmp_vdh_freq) {
        case 0:  //  0: VDH_F396M
            *vdh_freq = VDH_F396M;
            break;
        case 1:  //  1: VDH_F500M
            *vdh_freq = VDH_F500M;
            break;
        case 8:  //  8: VDH_F594M
            *vdh_freq = VDH_F594M;
            break;
        default:
            osal_printk("get PIPEBE1 freq %d error.\n", tmp_vdh_freq);
            return HI_FAILURE;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_set_vdec_freq(hi_vdh_freq vdh_freq)
{
    switch (vdh_freq) {
        case VDH_F396M:
            hi_reg_write32(0 << 13, 0x7 << 13, CRG_ADDR_MEDIA1);  //  0 << 13, 0x7 << 13: ?
            break;
        case VDH_F500M:
            hi_reg_write32(1 << 13, 0x7 << 13, CRG_ADDR_MEDIA1);  //  1 << 13, 0x7 << 13: ?
            break;
        case VDH_F594M:
            hi_reg_write32(2 << 13, 0x7 << 13, CRG_ADDR_MEDIA1);  //  2 << 13, 0x7 << 13: ?
            break;
        default:
            osal_printk("set VDH freq %d error.\n", vdh_freq);
            return MPP_EN_PM_ILLEGAL_PARAM;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_set_vdp_freq(hi_vdp_freq vdp_freq)
{
    switch (vdp_freq) {
        case VDP_F198M:
            hi_reg_write32(1 << 17, 0x1 << 17, CRG_ADDR_MEDIA3);  //  1 << 17, 0x1 << 17: ?
            break;
        case VDP_F300M:
            hi_reg_write32(0 << 17, 0x1 << 17, CRG_ADDR_MEDIA3);  //  0 << 17, 0x1 << 17: ?
            break;
        default:
            osal_printk("set VDP freq %d error.\n", vdp_freq);
            return MPP_EN_PM_ILLEGAL_PARAM;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_get_vdp_freq(hi_vdp_freq *vdp_freq)
{
    hi_u32 tmp_vdp_freq;
    hi_reg_read(&tmp_vdp_freq, CRG_ADDR_MEDIA3);
    tmp_vdp_freq &= (0x1 << 17);  //  0x1 << 17: ?
    tmp_vdp_freq >>= 17;  //  17: ?
    switch (tmp_vdp_freq) {
        case 1:  //  1: VDP_F198M
            *vdp_freq = VDP_F198M;
            break;
        case 0:  //  0: VDP_F300M
            *vdp_freq = VDP_F300M;
            break;
        default:
            osal_printk("get VDP freq %d error.\n", tmp_vdp_freq);
            return HI_FAILURE;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_get_avsp_freq(hi_avsp_freq *avsp_freq)
{
    hi_u32 tmp_avsp_freq;
    hi_reg_read(&tmp_avsp_freq, CRG_ADDR_MEDIA1);
    tmp_avsp_freq &= (0x7 << 13);  //  0x7 << 13: ?
    tmp_avsp_freq >>= 13;  //  13: ?
    switch (tmp_avsp_freq) {
        case 0:  //  0: AVSP_F300M
            *avsp_freq = AVSP_F300M;
            break;
        default:
            osal_printk("get VGS freq %d error.\n", tmp_avsp_freq);
            return HI_FAILURE;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_set_avsp_freq(hi_avsp_freq avsp_freq)
{
    switch (avsp_freq) {
        case AVSP_F300M:
            hi_reg_write32(0 << 16, 0x7 << 16, CRG_ADDR_MEDIA1);  //  0x7 << 16: ?
            break;
        default:
            osal_printk("set AVSP freq %d error.\n", avsp_freq);
            return MPP_EN_PM_ILLEGAL_PARAM;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_set_gdc_freq(hi_gdc_freq gdc_freq)
{
    switch (gdc_freq) {
        case GDC_F340M:
            hi_reg_write32(0 << 16, 0x7 << 16, CRG_ADDR_MEDIA1);  //  0 << 16, 0x7 << 16: ?
            break;
        case GDC_F400M:
            hi_reg_write32(2 << 16, 0x7 << 16, CRG_ADDR_MEDIA1);  //  2 << 16, 0x7 << 16: ?
            break;
        case GDC_F475M:
            hi_reg_write32(1 << 16, 0x7 << 16, CRG_ADDR_MEDIA1);  //  1 << 16, 0x7 << 16: ?
            break;
        default:
            osal_printk("set GDC freq %d error.\n", gdc_freq);
            return MPP_EN_PM_ILLEGAL_PARAM;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_get_gdc_freq(hi_gdc_freq *gdc_freq)
{
    hi_u32 tmp_gdc_freq;
    hi_reg_read(&tmp_gdc_freq, CRG_ADDR_MEDIA1);
    tmp_gdc_freq &= (0x7 << 16);  //  0x7 << 16: ?
    tmp_gdc_freq >>= 16;  //  16: ?
    switch (tmp_gdc_freq) {
        case 0:  //  0: GDC_F340M
            *gdc_freq = GDC_F340M;
            break;
        case 2:  //  2: GDC_F400M
            *gdc_freq = GDC_F400M;
            break;
        case 1:  //  1: GDC_F475M
            *gdc_freq = GDC_F475M;
            break;
        default:
            osal_printk("get GDC freq %d error.\n", tmp_gdc_freq);
            return HI_FAILURE;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_set_tde_freq(hi_tde_freq tde_freq)
{
    return HI_SUCCESS;
}

static hi_s32 pm_hal_get_tde_freq(hi_tde_freq *tde_freq)
{
    *tde_freq = TDE_F150M;
    return HI_SUCCESS;
}

static hi_s32 pm_hal_set_ai_ao_freq(hi_aiao_freq aiao_freq)
{
    switch (aiao_freq) {
        case AIAO_F1188M:
            hi_reg_write32(0 << 2, 0x3 << 2, CRG_ADDR_MEDIA4);  //  0 << 2, 0x3 << 2: ?
            break;
        case AIAO_F1500M:
            hi_reg_write32(1 << 2, 0x3 << 2, CRG_ADDR_MEDIA4);  //  1 << 2, 0x3 << 2: ?
            break;
        default:
            osal_printk("set AIAO freq %d error.\n", aiao_freq);
            return MPP_EN_PM_ILLEGAL_PARAM;
    }
    return HI_SUCCESS;
}

static hi_s32 pm_hal_get_ai_ao_freq(hi_aiao_freq *aiao_freq)
{
    hi_u32 tmp_aiao_freq;
    hi_reg_read(&tmp_aiao_freq, CRG_ADDR_MEDIA4);
    tmp_aiao_freq &= (0x3 << 2);  //  0x3 << 2: ?
    tmp_aiao_freq >>= 2; //  2: ?
    switch (tmp_aiao_freq) {
        case 0:
            *aiao_freq = AIAO_F1188M;
            break;
        case 1:
            *aiao_freq = AIAO_F1500M;
            break;
        default:
            osal_printk("get AIAO freq %d error.\n", tmp_aiao_freq);
            return HI_FAILURE;
    }
    return HI_SUCCESS;
}


hi_s32 set_media_freq_reg(const hi_media_freq *media_freq)
{
    hi_s32 i = 0;
    for (i = 0; i < VI_MAX_DEV_NUM; i++) {
        pm_hal_set_vicap_freq(media_freq->vi[0]);
    }
    pm_hal_set_vi_pipe_be_freq(media_freq->pipe_be);
    pm_hal_set_vgs_freq(media_freq->vgs);
    pm_hal_set_gdc_freq(media_freq->gdc);
    pm_hal_set_vpss_freq(media_freq->vpss);
    pm_hal_set_vedu_freq(media_freq->vedu);
    pm_hal_set_vdec_freq(media_freq->vdh);
    pm_hal_set_jpge_freq(media_freq->jpge);
    pm_hal_set_vdp_freq(media_freq->vdp);
    pm_hal_set_avsp_freq(media_freq->avsp);
    pm_hal_set_tde_freq(media_freq->tde);
    pm_hal_set_ai_ao_freq(media_freq->aiao);
    return HI_SUCCESS;
}

hi_s32 get_media_freq_reg(hi_media_freq  *media_freq)
{
    hi_s32 i = 0;
    for (i = 0; i < VI_MAX_DEV_NUM; i++) {
        pm_hal_get_vicap_freq(&media_freq->vi[i]);
    }
    pm_hal_get_vi_pipe_be_freq(&media_freq->pipe_be);
    pm_hal_get_vpss_freq(&media_freq->vpss);
    pm_hal_get_vedu_freq(&media_freq->vedu);
    pm_hal_get_vdec_freq(&media_freq->vdh);
    pm_hal_get_vdec_freq(&media_freq->vdh);
    pm_hal_get_jpge_freq(&media_freq->jpge);
    pm_hal_get_vgs_freq(&media_freq->vgs);
    pm_hal_get_gdc_freq(&media_freq->gdc);
    pm_hal_get_avsp_freq(&media_freq->avsp);
    pm_hal_get_vdp_freq(&media_freq->vdp);
    pm_hal_get_tde_freq(&media_freq->tde);
    pm_hal_get_ai_ao_freq(&media_freq->aiao);
    return HI_SUCCESS;
}


hi_s32 pm_hal_get_media_freq_by_usr_cfg(const hi_mpi_pm_media_cfg *pm_param, hi_media_freq *media_freq)
{
    int i = 0;
    hi_u32 au32_vipipe_sum_pixel = 0;
    if (media_freq == NULL) {
        osal_printk("pm_get_media_freq, media_freq is null.\n");
        return HI_FAILURE;
    }
    if (pm_param == NULL) {
        osal_printk("pm_get_media_freq, pm_param is null.\n");
        return HI_FAILURE;
    }
    for (i = 0; i < VI_MAX_DEV_NUM; i++) {
        if (pm_param->vi_cfg.au32_vicap_freq[i] <= 300) {  //  300 : vicap freq
            /*----according to the sensor ctrl.c cmos.c info ,to fill the vicap freq value-*/
            media_freq->vi[i] = VI_F300M;
        } else if (pm_param->vi_cfg.au32_vicap_freq[i] <= 340) {  //  340 : vicap freq
            /*----according to the sensor ctrl.c cmos.c info ,to fill the vicap freq value-*/
            media_freq->vi[i] = VI_F340M;
        } else if (pm_param->vi_cfg.au32_vicap_freq[i] <= 396) {  //  396 : vicap freq
            /*----according to the sensor ctrl.c cmos.c info ,to fill the vicap freq value-*/
            media_freq->vi[i] = VI_F396M;
        } else if (pm_param->vi_cfg.au32_vicap_freq[i] <= 500) {   //  500 : vicap freq
            /*----according to the sensor ctrl.c cmos.c info ,to fill the vicap freq value-*/
            media_freq->vi[i] = VI_F500M;
        } else if (pm_param->vi_cfg.au32_vicap_freq[i] <= 600) {  //  600 : vicap freq
            /*----according to the sensor ctrl.c cmos.c info ,to fill the vicap freq value-*/
            media_freq->vi[i] = VI_F600M;
        }
    }
    /*-------PIPE BE freq----*/
    for (i = 0; i < VI_MAX_PHY_PIPE_NUM; i++) {
        au32_vipipe_sum_pixel += pm_param->vi_cfg.au32_vipipe_sum_pixel[i];
    }
    if (au32_vipipe_sum_pixel <= 300) {   //  300 : sum pixel
        media_freq->pipe_be = PIPEBE_F300M;
    } else if (au32_vipipe_sum_pixel <= 340) {   //  340 : sum pixel
        media_freq->pipe_be = PIPEBE_F340M;
    }
    /*----vpss freq---*/
    if (pm_param->vpss_sum_pix <= 300) {   //  300 : sum pixel
        media_freq->vpss = VPSS_F300M;
    } else if (pm_param->vpss_sum_pix <= 396) {   //  396 : sum pixel
        media_freq->vpss = VPSS_F396M;
    }
    /*----venc freq---*/
    if (pm_param->venc_sum_pix <= 396) {   //  396 : sum pixel
        media_freq->vedu = VEDU_F396M;
    }
    /*----vdec freq---*/
    if (pm_param->vdec_sum_pix <= 396) {    //  396 : sum pixel
        //media_freq->vedu= VDH_F396M;
    }
    /*----avsp freq---*/
    if (pm_param->avsp_sum_pix <= 300) {   //  300 : sum pixel
        media_freq->avsp = AVSP_F300M;
    }
    return HI_SUCCESS;
}


hi_s32 pm_hal_set_media_freq_by_usr_cfg(const hi_mpi_pm_media_cfg *usr_param)
{
    hi_media_freq media_freq = {};
    pm_hal_get_media_freq_by_usr_cfg(usr_param, &media_freq);
    set_media_freq_reg(&media_freq);
    return HI_SUCCESS;
}


void pm_hal_get_media_profile(hi_media_freq *media_freq, hi_u32  *profile)
{
    hi_s32 i = 0;
    hi_u32 tmp_profile = 0;
    hi_media_freq tmp_media_freq = {};
    osal_memcpy(&tmp_media_freq, media_freq, sizeof(hi_media_freq));
    for (i = 0; i < 3; i++) {

        if (tmp_media_freq.vgs > media_profile[i].vgs) {
            continue;
        }
        if (tmp_media_freq.gdc > media_profile[i].gdc) {
            continue;
        }
        if (tmp_media_freq.vpss > media_profile[i].vpss) {
            continue;
        }
        if (tmp_media_freq.vedu > media_profile[i].vedu) {
            continue;
        }
        if (tmp_media_freq.jpge > media_profile[i].jpge) {
            continue;
        }
        if (tmp_media_freq.vdp > media_profile[i].vdp) {
            continue;
        }
        if (tmp_media_freq.tde > media_profile[i].tde) {
            continue;
        }

        tmp_profile = i + 1;
        *profile = tmp_profile;
        break;
    }
    return ;
}

hi_s32 pm_hal_get_media_profile_by_usr_cfg(hi_mpi_pm_media_cfg *usr_param, hi_u32  *profile)
{
    hi_s32 i = 0;
    hi_u32 tmp_profile = 0;
    hi_media_freq media_freq = {};
    pm_hal_get_media_freq_by_usr_cfg(usr_param, &media_freq);
    for (i = 0; i < 3; i++) {

        if (media_freq.vgs > media_profile[i].vgs) {
            continue;
        }
        if (media_freq.gdc > media_profile[i].gdc) {
            continue;
        }
        if (media_freq.vpss > media_profile[i].vpss) {
            continue;
        }
        if (media_freq.vedu > media_profile[i].vedu) {
            continue;
        }
        if (media_freq.jpge > media_profile[i].jpge) {
            continue;
        }
        if (media_freq.vdp > media_profile[i].vdp) {
            continue;
        }
        if (media_freq.tde > media_profile[i].tde) {
            continue;
        }
        tmp_profile = i + 1;
        break;
    }
    *profile = tmp_profile;
    return HI_SUCCESS;
}

